Split-gate flash technology has been widely employed in medium-low density applications. Conventional split-gate flash memory density is difficult to scale without introducing cell reliability and performance issues. Efforts have been made to enhance cell reliability and performance. For example, bit cell 100a in FIG. 1A (depicting a pair of identical memory bit cells formed on an upper surface of substrate 101 and sharing a common source (S)), including charge-storage layer 103a, salicide (self-aligned silicide) 105a, and sidewall spacers 107a, utilizes an overlap between control gate (CG) 109a and select gate (SG) 111a to avoid the easy CG-SG breakdown induced by the salicide process. Bit cell 100b in FIG. 1B, including CG 109b, SG 111b, charge-storage layer 103b, and salicide 105b, has a relatively simpler fabrication process because there is no CG-SG overlap. However, SG-CG breakdown voltage and cell reliability are poor.
These approaches are problematic for scaling to high-density applications in several respects. For example, a complex and costly three-mask lithography process must be utilized to form the overlapping gate structure of bit cell 100a. Alignment of the three masks is critical; any misalignment of the polysilicon layers used to form the gates results in CG 109a overlapping SG 111a by too much or too little. Too much overlap will minimize the salicide 105a formed over SG 111a. If the overlap is insufficient, poor isolation between CG 109a and SG 111a results, thereby decreasing the breakdown voltage between the gates. Employing the non-overlapping gate structure of bit cell 100b simplifies the fabrication process, but is costly because an additional chemical-mechanical polishing (CMP) step must be utilized to planarize the polysilicon of CG 109b and SG 111b. 
Bit cell 100c in FIG. 1C illustrates a conventional floating gate (FG) split-gate NVM design. FG 113 and CG 109c, separated by interpoly dielectric (IPD) 115, form a dual polysilicon gate stack on tunnel oxide 117 that is separated from SG 111c by interpoly oxide (IPO) 119. SG 111c is formed through a polysilicon spacer etch process. No silicide is formed in the NVM region, causing high contact resistance on the source and rain area and, therefore, degraded electrical performance. In addition, processing of the device is costly because the 2-polysilicon height of the dual gate stack creates a difference in topology between the NVM and logic circuit sections. Thus, an additional mask must be used to protect the NVM array during etching of the logic sections.
A need therefore exists for methodology enabling fabrication of a split-gate NVM device exhibiting enhanced cell reliability and electrical performance in high-density applications, and for the resulting device.